We build FPGA-accelerated signal processing, post-quantum cryptographic hardware, and trustworthy edge autonomy for resource-constrained platforms operating in contested environments — from UAV swarms to spacecraft to edge microclusters.
From tilt-rotor airframes to FPGA microclusters — we work across the full stack of edge autonomy hardware. Real platforms, real specs, real flight time.
Tilt-rotor architecture for extended-endurance ISR and contested-airspace operation. Vertical takeoff and landing combined with fixed-wing efficiency in cruise.
Quadcopter formations using blade-pass acoustic tones for RF-silent intra-swarm communication. The HORUS approach to GPS- and RF-denied coordination.
Heterogeneous edge cluster combining ARM compute, FPGA acceleration, and AI-class GPU inference. The KHEPRI / KHONSU / SESHAT runtime substrate.
Four real systems from our published work. Each one brings together reconfigurable silicon, distributed runtime, and cryptographic discipline for a different operational reality.
Each NMEA sentence becomes a first-class cryptographic object. 99.80% acceptance over an 810-second live capture, ~25 ms end-to-end latency at 200 packets/s, ~7 W cluster draw. ~30% lower energy per packet than AES-GCM.
Per-window Merkle commitments for off-node verification. Keepalive (no consecutive misses) and Hot-Swap (recovery within one cadence) under injected failover. 11/11 trials recovered within 10 s.
Two AUP-ZU3 workers, eight hardware lanes. Stable streaming shell with swappable XOF units. Worker-side phase times 2.3–2.7 ms across LMS, XMSS, and SPHINCS+. 300–330 MHz operation.
Stateless and stateful Merkle-tree signature schemes accelerated on a unified XOF substrate. Hash-based security reduces to standard hash assumptions — conservative, audit-ready, post-quantum.
Real diagrams, real hardware, real fielded research. The block diagrams from our published papers, the posters from our presentations, and the award certificates that say the work is good.
The KHONSU hardware architecture distributes hash/XOF work across four parallel lanes per worker, decoupled by AXI4-Stream FIFOs. Each lane runs in CHAIN mode (32→32 byte hash chaining) or MERGE_CHAIN mode (64→32 byte node compression). A Verilog RTL collector repacketizes lane outputs back to a single S2MM stream, isolating the lanes from DMA backpressure.
The full conference poster from GomacTech 2026, presenting our trusted microelectronic stack for NLP-controlled UAV swarms operating in GPS-denied and electronically contested environments. Memory-safe Rust firmware, ASCON authenticated encryption, post-quantum ML-KEM provisioning, hybrid FPGA/FPAA TRNG, and dual-link communications (ExpressLRS primary, LoRa fallback) — designed to deliver mission integrity under jamming and C2 denial.
Australian Automation and Robotics Precinct (AARP), Perth, Australia. RSC Lab Team led by Dr. El-Hadedy successfully tele-operated a rover with full telemetry on simulated lunar terrain — competing internationally against teams from across robotics and aerospace research.
Most autonomous systems are software stacks waiting to be compromised. We design from silicon up: reconfigurable computing fabrics, cryptographic primitives, and signal processing kernels that hold their integrity in contested environments.
FPGA, ARM, and RISC-V architectures for real-time signal processing, cryptographic hashing, and AI inference under strict latency and power constraints. Multi-clock-domain optimization. HLS+RTL co-design with deterministic streaming shells.
Lightweight cryptography on embedded hardware. Stateful and stateless hash-based signatures (LMS, XMSS, SLH-DSA / SPHINCS+). Tamper-evident sensor pipelines. Rust-driven firmware with hardware roots of trust.
NLP-controlled UAV swarms with edge AI inference on Kubernetes microclusters. Acoustic intra-swarm coordination for GPS- and RF-denied operation. Reflexive, self-healing autonomy under stress.
Post-quantum security on FPGA, ARM, and RISC-V embedded platforms for IoT and UAV systems.
Heterogeneous architectures for high-performance signal processing, DNA alignment, and AI inference.
Multi-physics simulation frameworks. Earth Lookback Simulator, physiological adaptation modeling.
NLP-controlled UAV swarms, Kubernetes-orchestrated edge clusters, hardware-rooted telemetry integrity.
A complete record from 2006 forward. 741 citations, h-index 14, i10-index 19. Including accepted papers not yet indexed.
"I want my hardware to deserve its name. If a system is called HORUS, then it had better watch. If it is called MA'AT, it had better keep order. The naming is a promise to the people who depend on it."
Dr. Mohamed El-Hadedy is the founder and CEO of RecoIoT LLC and a tenured Associate Professor in the Department of Electrical & Computer Engineering at California State Polytechnic University, Pomona, where he directs the Reconfigurable Space Computing Lab (RSCL@CPP).
His research sits at the intersection of reconfigurable computing, embedded security, flight software, and mission-driven autonomy. What makes the work distinctive is that it does not stop at algorithms or simulations — it produces complete systems: FPGA and MPSoC prototypes, Kubernetes/edge testbeds, flight-software integrations, drone platforms, cryptographic services, sensor pipelines, and defense-relevant autonomy experiments. SEKHMET won Best Paper at NG-RES 2026/HiPEAC. HORUS turns unavoidable multirotor blade-pass noise into an acoustic side-channel for GPS- and RF-denied swarm awareness. MEHEN (under review at IEEE Space Computing) makes programmable fabric the backend of an F′ flight-software security component — not just hardware acceleration, but operationally visible security services integrated into real flight workflows. The core pattern across the work is capability creation, not incremental exercises.
Mohamed earned his Ph.D. from the Norwegian University of Science and Technology (NTNU), with a dissertation in cryptographic hardware co-design. He holds a Master's and Bachelor's in Electronics Engineering from Mansoura University, Egypt. Before academic research, from 2004 to 2008, he served as a Research Scientist at the Egyptian Nuclear Research Reactor — a foundation that informs his ongoing work on radiation-tolerant computing, single-event-effects (SEE), and trustworthy electronics for space.
After NTNU he joined Atmel Norway AS as a Senior Design Engineer, working on production microcontroller and FPGA silicon — the industry foundation that grounds every prototype RecoIoT builds today in real chip-design discipline. He then returned to academia as Postdoctoral Fellow at the University of Virginia and Senior Research Scientist at the University of Illinois Urbana-Champaign (UIUC) in collaboration with Wen-Mei Hwu. RecoIoT LLC was founded in 2017 to translate that research-and-industry lineage into deliverable hardware for U.S. defense and space programs.
His record shows sustained, mission-aligned achievement: continuous federal support since 2017 from the Air Force Research Laboratory, U.S. Army Research Office, U.S. Navy NEEC and ONR, NSWC Corona, NASA, and Lawrence Berkeley National Lab — cumulative awards exceeding $5 million. Three issued U.S. patents in reconfigurable cryptographic processing and transposition-memory architecture, plus a fourth filed for a compliant inspection mechanism developed at Los Alamos National Laboratory. Three Best Paper Awards across NG-RES/HiPEAC 2026, RAW/IPDPS 2016, and SRC TECHCON 2016. Third Place at the 2025 IEEE Telepresence Competition in Perth, Australia. Invited talks at LBNL in 2024 and 2025. More than seventy peer-reviewed papers. Mentor of multiple NASA MINDS finalist and award-winning teams. Senior Member of both IEEE and ACM.
His operating thesis is straightforward: the strongest defense systems are not the ones with the most software, but the ones with the most verifiable silicon — hardware that can be reasoned about, audited, and trusted at the component level. RecoIoT is built around that belief.
We're always open to honest conversations — about SBIR/STTR collaborations, federal research partnerships, edge deployments, or just hard problems in reconfigurable computing, post-quantum cryptography, or trustworthy autonomy. If something here resonates with what you're building, write to us.