RecoIoT LLC · est. 2017 · Pomona, California

Reconfigurable computing for the Internet of Things.

RecoIoT  =  Reconfigurable Internet of Things

We build FPGA-accelerated signal processing, post-quantum cryptographic hardware, and trustworthy edge autonomy for resource-constrained platforms operating in contested environments — from UAV swarms to spacecraft to edge microclusters.

Founded 2017 SBC SBC_002671100 Domain Embedded · UAV · Space
VTOL · TILT-ROTOR · ACOUSTIC SWARM CARRIER SCENE 01 / VTOL QUADCOPTER SWARM · ACOUSTIC INTRA-LINK SCENE 02 / SWARM ARM A53 FPGA SHAKE256 LANES AUP-ZU3 · WORKER 1 ARM A53 FPGA SHAKE256 LANES AUP-ZU3 · WORKER 2 AXI DMA 2× AUP-ZU3 · 8 HARDWARE LANES · POST-QUANTUM SCENE 03 / CLUSTER
— Platforms

Three classes of platform. One reconfigurable substrate.

From tilt-rotor airframes to FPGA microclusters — we work across the full stack of edge autonomy hardware. Real platforms, real specs, real flight time.

01 / Aerial

VTOL hybrid

Tilt-rotor · Long endurance

Tilt-rotor architecture for extended-endurance ISR and contested-airspace operation. Vertical takeoff and landing combined with fixed-wing efficiency in cruise.

Frame Custom tilt-rotor airframe
FC Pixhawk 6X · PX4
Compute Jetson Orin Nano · onboard AI
Range 5–25 km (cruise)
02 / Aerial

Multirotor swarm

Quadcopter · Acoustic intra-link

Quadcopter formations using blade-pass acoustic tones for RF-silent intra-swarm communication. The HORUS approach to GPS- and RF-denied coordination.

Frame Holybro X500 V2
FC Pixhawk 6X · PX4
Mic Array ReSpeaker 6-mic circular
Range 10–150 m (close formation)
03 / Compute

Edge microcluster

FPGA · ARM · Heterogeneous
PI 4 AUP-ZU3 JETSON CLUSTERHAT · ETHERNET BUS

Heterogeneous edge cluster combining ARM compute, FPGA acceleration, and AI-class GPU inference. The KHEPRI / KHONSU / SESHAT runtime substrate.

Controller Raspberry Pi 4
FPGA Worker AUP-ZU3 (Zynq UltraScale+)
AI Worker Jetson Orin Nano
Bus ClusterHAT v2.5 · Ethernet
— Sensor Stack

Real-time perception, hardware-rooted.

RPLIDAR A2

Rotating · 360°

u-blox F9P

GNSS · PPS · RTK
Z X Y

BMI088 IMU

6-axis · 1.6 kHz

ReSpeaker 6-mic

MEMS · DOA · Beamform
— Build of Materials
Holybro X500 V2 Pixhawk 6X PX4 Autopilot Jetson Orin Nano TuringPi 2 AUP-ZU3 Zynq UltraScale+ MPSoC ClusterHAT v2.5 Raspberry Pi 4 / Zero 2 W ReSpeaker 6-mic Array RPLIDAR A2 u-blox F9P GNSS BMI088 IMU ExpressLRS Link LoRa Fallback
— Systems We Build

Hardware-rooted architectures, in motion.

Four real systems from our published work. Each one brings together reconfigurable silicon, distributed runtime, and cryptographic discipline for a different operational reality.

— HOURS / GomacTech

UAV swarm telemetry, sealed at the source.

ASCON-128A · MQTT · ARM64 cluster

Each NMEA sentence becomes a first-class cryptographic object. 99.80% acceptance over an 810-second live capture, ~25 ms end-to-end latency at 200 packets/s, ~7 W cluster draw. ~30% lower energy per packet than AES-GCM.

ASCON-128A · MQTT · QoS 1 99.80% INTEGRITY
— KHEPRI

Edge microclusters with verifiable perception.

Pi 4 controller · 4× Pi Zero 2 W · ClusterHAT

Per-window Merkle commitments for off-node verification. Keepalive (no consecutive misses) and Hot-Swap (recovery within one cadence) under injected failover. 11/11 trials recovered within 10 s.

PI 4 · CONTROLLER ZERO 2W ZERO 2W ZERO 2W ZERO 2W GPS/PPS
— KHONSU / SESHAT

ARM+FPGA SoC with 8-lane hash offload.

Zynq UltraScale+ AUP-ZU3 · DMA · SHAKE256

Two AUP-ZU3 workers, eight hardware lanes. Stable streaming shell with swappable XOF units. Worker-side phase times 2.3–2.7 ms across LMS, XMSS, and SPHINCS+. 300–330 MHz operation.

ARM CORTEX-A53 SCHEDULER DMA FPGA · 8 LANES SHAKE 256 DATA PLANE
— SESHAT / KHONSU

Post-quantum signatures, hash by hash.

SLH-DSA (SPHINCS+) · LMS · XMSS

Stateless and stateful Merkle-tree signature schemes accelerated on a unified XOF substrate. Hash-based security reduces to standard hash assumptions — conservative, audit-ready, post-quantum.

ROOT SHA-256 · SHAKE256 · DOMAIN-SEPARATED HASHES
— Architecture & Showcase

From paper to silicon. From silicon to flight.

Real diagrams, real hardware, real fielded research. The block diagrams from our published papers, the posters from our presentations, and the award certificates that say the work is good.

— Featured Architecture · KHONSU

Per-AUP-ZU3 worker, single-DMA streaming shell.

HEART 2026 · Heidelberg

The KHONSU hardware architecture distributes hash/XOF work across four parallel lanes per worker, decoupled by AXI4-Stream FIFOs. Each lane runs in CHAIN mode (32→32 byte hash chaining) or MERGE_CHAIN mode (64→32 byte node compression). A Verilog RTL collector repacketizes lane outputs back to a single S2MM stream, isolating the lanes from DMA backpressure.

LUT 47,460 · 67% utilization
FF 61,086 · 43% utilization
BRAM 40.5 · 19% utilization
Frequency 300–330 MHz internal
Total 8 hardware lanes across two AUP-ZU3 boards
KHONSU hardware architecture: ARM PS, AXI DMA, RTL distributor, four HLS hash lanes, AXI-Stream FIFOs, Verilog collector, output FIFO
— Conference Poster · GomacTech 2026

Trusted microelectronics for NLP-controlled UAV swarms.

DoD GomacTech 2026 · Distribution A

The full conference poster from GomacTech 2026, presenting our trusted microelectronic stack for NLP-controlled UAV swarms operating in GPS-denied and electronically contested environments. Memory-safe Rust firmware, ASCON authenticated encryption, post-quantum ML-KEM provisioning, hybrid FPGA/FPAA TRNG, and dual-link communications (ExpressLRS primary, LoRa fallback) — designed to deliver mission integrity under jamming and C2 denial.

Authors Mohamed El-Hadedy · Benny Cheng (NSWC Corona)
Funding AFRL · U.S. Navy / NAVSEA
Status Distribution A · Approved for Public Release
Trusted Microelectronics for NLP-Controlled UAV Swarms in Contested Environments — full GomacTech 2026 poster with mission need, threat model, system stack, and degradation control states
2025 IEEE Telepresence Competition Third Place certificate awarded to Mohamed El-Hadedy and the RSC Lab Team for tele-operating a rover with full telemetry on simulated lunar terrain in Perth, Australia
— International Award

3rd Place · 2025 IEEE Telepresence Competition

Australian Automation and Robotics Precinct (AARP), Perth, Australia. RSC Lab Team led by Dr. El-Hadedy successfully tele-operated a rover with full telemetry on simulated lunar terrain — competing internationally against teams from across robotics and aerospace research.

— What We Do

Hardware-rooted intelligence for the edge.

Most autonomous systems are software stacks waiting to be compromised. We design from silicon up: reconfigurable computing fabrics, cryptographic primitives, and signal processing kernels that hold their integrity in contested environments.

01 / Silicon

Reconfigurable computing & FPGA-accelerated DSP.

FPGA, ARM, and RISC-V architectures for real-time signal processing, cryptographic hashing, and AI inference under strict latency and power constraints. Multi-clock-domain optimization. HLS+RTL co-design with deterministic streaming shells.

02 / Trust

Post-quantum security for autonomous platforms.

Lightweight cryptography on embedded hardware. Stateful and stateless hash-based signatures (LMS, XMSS, SLH-DSA / SPHINCS+). Tamper-evident sensor pipelines. Rust-driven firmware with hardware roots of trust.

03 / Autonomy

Decentralized intelligence in denied environments.

NLP-controlled UAV swarms with edge AI inference on Kubernetes microclusters. Acoustic intra-swarm coordination for GPS- and RF-denied operation. Reflexive, self-healing autonomy under stress.

— Active Programs

Named for the watchers, the scribes, the protectors.

Each system carries a name from the Egyptian pantheon. HORUS watches. THOTH records. ANUBIS measures. MA'AT keeps order. SESHAT writes the truth. Hardware that lives up to its name.
𓅃
HORUSAcoustic Swarm Communication
RF-silent intra-swarm communication and relative localization for sUAS in GPS- and RF-denied environments. Blade-pass tone modulation, MEMS array signal processing, decentralized Boids control.
2026 · SOCOM
𓁟
THOTHPost-Quantum Edge Orchestration
Reliable orchestration of post-quantum secure communication across multi-architecture edge clusters. Rust-driven firmware, HDL co-design, K3s-native trust roots.
2025 · ISSREW
𓃣
ANUBISTrue Random Number Generation
Hybrid FPAA-FPGA architecture for entropy-based TRNG in secure UAV communication. The trusted entropy foundation under every cryptographic service.
2025 · IEEE ESL
𓊪
MA'ATDeterministic Telemetry Integrity
FPGA-assisted dual-core architecture for deterministic IoT telemetry integrity. Hash-chained perception contracts at line rate.
2025 · MILCOM
𓋹
SEKHMETHash-Chained Perception
Hash-chained perception contracts for heterogeneous real-time edge clusters. Best Paper Award, NG-RES / HiPEAC 2026, Krakow.
2026 · Best Paper
𓆣
KHEPRIVerifiable Perception Windows
Verifiable perception windows with keepalive and hot-swap recovery on Pi-class edge microclusters. PPS-disciplined, Merkle-committed, independently checkable.
2026 · SCV
𓂀
KHONSUHash Offload Network
Kernel hash offload network of swappable units for post-quantum signatures. Two AUP-ZU3 workers, eight lanes, unified LMS/XMSS/SPHINCS+ runtime.
2026 · HEART
𓊽
SESHATSpacecraft Cryptographic Service Plane
A spacecraft cryptographic service plane on ARM+FPGA SoCs. Trusted entropy, DMA-backed SHAKE256 lanes, SLH-DSA authentication. Cryptography as a system-level service.
2026 · MAPLD
𓈗
RA-SRFPGA Multi-Protocol ESC Controller
16–32 channel low-power FPGA multi-protocol ESC controller for space robotics. The hardware foundation that makes acoustic-domain UAV control feasible.
2025 · IEEE Space Computing
𓇼
KEPLER-452bNASA ORBIT · Reconfigurable Space Computing Lab
Phase 2 advancement in NASA's ORBIT Space Track challenge — designing system concepts for sustainable lunar presence, in-situ resource utilization, and Artemis-aligned deep-space missions. Phase 2 submission video →
2026 · NASA
— Research Thrusts

Five intersecting fields. One operating thesis.

01

Lightweight cryptography

Post-quantum security on FPGA, ARM, and RISC-V embedded platforms for IoT and UAV systems.

02

Reconfigurable computing

Heterogeneous architectures for high-performance signal processing, DNA alignment, and AI inference.

03

GPU-accelerated simulation

Multi-physics simulation frameworks. Earth Lookback Simulator, physiological adaptation modeling.

04

Trustworthy edge autonomy

NLP-controlled UAV swarms, Kubernetes-orchestrated edge clusters, hardware-rooted telemetry integrity.

741
Citations
14
h-index
3
Issued patents
$5M+
Active federal funding
— Trusted by
U.S. Air Force Research Laboratory U.S. Army Research Office U.S. Navy NEEC / ONR NSWC Corona NASA Lawrence Berkeley National Lab USAFA
— Publications

Two decades. Sixty-plus papers. Four patents.

A complete record from 2006 forward. 741 citations, h-index 14, i10-index 19. Including accepted papers not yet indexed.

2026 · 9 entries
[01]
SEKHMET: Hash-Chained Perception Contracts for Heterogeneous Real-Time Edge Clusters
El-Hadedy, M.
NG-RES / HiPEAC · Krakow
Best Paper
[02]
KHONSU: Kernel Hash Offload Network of Swappable Units for Post-Quantum Signatures
El-Hadedy, M.
HEART · Heidelberg
Accepted
[03]
SESHAT: A Spacecraft Cryptographic Service Plane on ARM+FPGA SoCs
El-Hadedy, M.
MAPLD
To be presented
[04]
HOURS: Lightweight, Orchestrated Security for UAV Swarm Telemetry
El-Hadedy, M.
IEEE PERCOM
SPT-IoT · Pisa
[05]
KHEPRI: Verifiable Perception Windows with Keepalive and Hot-Swap Recovery on Edge Microclusters
El-Hadedy, M.
SCV
Accepted
[06]
Trusted Microelectronics for NLP-Controlled UAV Swarms in Contested Environments
El-Hadedy, M., Cheng, B.
GomacTech
Presented
[07]
SESHAT: Systematic Energy & Seed-Provenance Harness for Algorithmic Tradeoffs
El-Hadedy, M.
IEEE ESL
Journal
[08]
RSCL Earth Lookback Simulator: Real-Time Multi-Physics Framework for Relativistic Signal Propagation from Confirmed Milky Way Exoplanets
El-Hadedy, M.
arXiv
Preprint
[09]
NEITH: Networked Evidence Integrity for Telemetry Hashing
El-Hadedy, M.
IEEE SaTC
Accepted
2025 · 9 entries
[09]
ANUBIS: Hybrid FPAA-FPGA Architecture for Entropy-Based True Random Number Generation in Secure UAV Communication
El-Hadedy, M., Abelian, A., Lee, K., Cheng, B. N., Hwu, W.-M.
IEEE ESL
Vol. 17 · No. 3
[10]
Ma'at: FPGA-Assisted Dual-Core Architecture for Deterministic IoT Telemetry Integrity
El-Hadedy, M., Hwu, W.-M., Cheng, B.
MILCOM
Los Angeles
[11]
RA-SR: A 16–32-Channel Low-Power FPGA Multi-Protocol ESC Controller for Space Robotics
El-Hadedy, M., Reynard, L., Guerrieri, A., Cheng, B., Hwu, W.-M.
IEEE Space Computing
Los Angeles
[12]
HORUS: Hash-Oriented Resilient Unforgeable Sensing — Tamper-Evident Sensor Telemetry on Edge Microclusters
El-Hadedy, M.
ICM
Cairo
[13]
Thoth: Rust-Driven Firmware and HDL Co-Design for Trusted IoT/UAV Systems
El-Hadedy, M., Hwu, W.-M.
NorCAS
Riga
[14]
Thoth: Reliable Orchestration of Post-Quantum Secure Communication in Multi-Architecture Edge Clusters
El-Hadedy, M., Hwu, W.-M.
IEEE ISSREW
São Paulo
[15]
QuickCommand: A Low-Latency NLP Pipeline for Reliable UAV Telepresence code & data →
El-Hadedy, M., Hwu, W.-M. — 19 ms median E2E latency, 100% accuracy on CPU-only Quantized-BERT
ReSAISE / ISSREW
São Paulo
[16]
Ptah: Teaching Computer Architecture through NLP-Controlled Drones with Edge AI and Kubernetes
El-Hadedy, M., Cheng, B., Hwu, W.-M.
ACM WCAE
Tokyo
[17]
Ra: Long-Range FPGA Streaming and Dynamic Partial Reconfiguration Over LoRa with RISC-V MicroBlaze Watchdog
El-Hadedy, M., Hwu, W.-M., Cheng, B.
SEE/MAPLD
San Diego · Oral
[★]
3rd Place — IEEE Telepresence Competition 2025
El-Hadedy, M. & RSC Lab Team — Tele-operating a rover with full telemetry on simulated lunar terrain
IEEE Telepresence
Perth, Australia
2024 · 5 entries
[17]
Reconfigurable Crypto-Processor
El-Hadedy, M., Hwu, W.-M., Skadron, K. — U.S. Patent 11,977,883 B2 — Issued May 7, 2024
Patent
UVA · UIUC
[18]
SENTINEL: Scalable Edge Network for Telepresence and Integrated AI
El-Hadedy, M., Ung, J., Kim, D., Hwu, W.-M., He, Y., Cheng, B.
IEEE Telepresence
Pasadena
[19]
Securing the Internet of Medical Things with K3S and Hybrid Cryptography
El-Hadedy, M., Ankunda, P., Ung, J., Hwu, W.-M.
IEEE DCAS
Richardson
[20]
Optimizing ASCON Permutation in Multi-Clock Domains with Chisel
El-Hadedy, M., Hua, R., Yoshii, K., Hwu, W.-M.
IEEE DCAS
Richardson
[21]
Revolutionizing UAV Control: Integrating NLP with Advanced FPGA and FPAA Technologies for Dynamic Reconfigurability
El-Hadedy, M., Abelian, A., Ung, J., Cheng, B., Hwu, W.-M.
SEE/MAPLD
La Jolla
2023 · 4 entries
[22]
RECO-ASCON: Reconfigurable ASCON Hash Functions for IoT Applications
El-Hadedy, M., Guo, X., Yoshii, K., Cai, Y., Herndon, R., Banta, B., Hwu, W.-M.
Elsevier Integration
Vol. 93 · Journal
[23]
BLTESTI: Benchmarking Lightweight TinyJAMBU on Embedded Systems for Trusted IoT
El-Hadedy, M., Hua, R., Saqib, S., Yoshii, K., Hwu, W.-M., Margala, M.
IEEE SoCC
Santa Ana
[24]
RECO-LFSR: Reconfigurable Low-Power Cryptographic Processor Based on LFSR for Trusted IoT
El-Hadedy, M., Hua, R., Yoshii, K., Hwu, W.-M., Margala, M.
IEEE ISQED
Conference
[25]
SHRECO-HRCT: Self-Healing Reconfigurable High-Throughput Compact TinyJAMBU Processor for Trusted IoT
El-Hadedy, M., Margala, M., Hwu, W.-M.
SEE/MAPLD
La Jolla
2022 · 5 entries
[24]
Agile-AES: Implementation of Configurable AES Primitive with Agile Design Approach
Guo, X.*, El-Hadedy, M.*, Mosanu, S., Wei, X., Skadron, K., Stan, M.
Elsevier Integration
VLSI · Vol. 85
[25]
RECO-HCON: A High-Throughput Reconfigurable Compact ASCON Processor for Trusted IoT
Wei, X.*, El-Hadedy, M.*, Mosanu, S., Zhu, Z., Hwu, W.-M., Guo, X.
IEEE SoCC
Belfast
[26]
ReaLSE: Reconfigurable Lightweight Security Engines for Trusted Edge Devices
El-Hadedy, M., Guo, X.
IEEE ICCS
Chengdu
[27]
RECO-ASCON: Reconfigurable Lightweight ASCON Hash Functions for IoT
El-Hadedy, M., Yoshii, K., Formicola, V., Guo, X., Hwu, W.-M.
CCF Chip
Nanjing
[28]
Post-Quantum Stateful Hash-Based Signature Scheme for Improved Bluetooth Security
El-Hadedy, M., Formicola, V., Hwu, W.-M.
SEE / MAPLD
La Jolla
2021 · 4 entries
[30]
PRO-GAGE: A High-Performance Compact GAGE Hash Function Processor for Small Space Technology
El-Hadedy, M., Margala, M., Mosanu, S., Gligoroski, D., Xiong, J.
IEEE Space Computing
Conference
[31]
SHA-3-LPHP: Hardware Acceleration of SHA-3 for Low-Power High-Performance Systems
Akiya, Y., et al., El-Hadedy, M.
ISSRE
Wuhan
[32]
Reco-GAGE: A Reconfigurable Lightweight GAGE Hash Function Engine for IoT Devices
El-Hadedy, M.
SEE/MAPLD
La Jolla
[33]
Design and Simulation of Bitcoin Mining and Implementation on ZYBO Z7-20 FPGA
El-Hadedy, M.
SEE/MAPLD
La Jolla
2020 · 5 entries
[34]
Memory Systems Including Support for Transposition Operations and Related Methods and Circuits
El-Hadedy, M., Skadron, K. — U.S. Patent 10,664,241 B2 — Issued May 26, 2020
Patent
UVA
[35]
MICRO-GAGE: A Low-Power Compact GAGE Hash Function Processor for IoT
El-Hadedy, M., Margala, M., Mosanu, S., Gligoroski, D., Xiong, J., Hwu, W.-M.
IEEE ICECS
Glasgow (Virtual)
[36]
Evaluating Post-Quantum Cryptographic Algorithms on Quantum Machines
El-Hadedy, M.
Quantum U Tech Accelerator
Million Dollar Intl
[37]
Performance Evaluation of Wide-Range AI Applications on Raspberry Pi
El-Hadedy, M.
SEE/MAPLD
La Jolla
[38]
Reconfigurable Image Processing Applications on FPGAs
El-Hadedy, M., Salah Eddin, A., El-Naga, H.
SEE/MAPLD · Poster
La Jolla
2019 · 5 entries
[39]
Reco-Pi: A Reconfigurable Cryptoprocessor for Pi-Cipher
El-Hadedy, M., Kulkarni, A., Stroobandt, D., Skadron, K.
JPDC
Vol. 133 · Journal
[40]
Analysis and Modeling of Collaborative Execution Strategies for Heterogeneous CPU-FPGA Architectures
Huang, S., et al., El-Hadedy, M.
ICPE
Conference
[41]
Flexi-AES: A Highly-Parameterizable Cipher for a Wide Range of Design Constraints
Mosanu, S., Guo, X., El-Hadedy, M., et al.
IEEE FCCM
Conference
[42]
RECO-CRYPT: Reconfigurable Crypto-Processor for Small Electronics
El-Hadedy, M., Anjum, O., Hwu, W.-M.
SRC TECHCON
Austin
[43]
Low-Power High-Performance Reconfigurable Computing Using FPGA
El-Hadedy, M.
SEE/MAPLD
La Jolla
2018 · 3 entries
[38]
A Compliant Mechanism for Inspecting Extremely Confined Spaces
Mascarenas, D., et al., El-Hadedy, M. — Patent Filed Oct 25, 2018
Patent
LANL
[39]
ASAP: Accelerated Short-Read Alignment on Programmable Hardware
Banerjee, S. S., El-Hadedy, M., Lim, J., Kalbarczyk, Z., Chen, D., Lumetta, S., Iyer, R.
IEEE Trans. Computers
Journal
[40]
Triangle Counting and Truss Decomposition using FPGA
Huang, S., El-Hadedy, M., et al.
IEEE HPEC
Conference
2017 · 7 entries
[41]
Dual-Data Rate Transpose-Memory Architecture Improves the Performance, Power and Area of Signal-Processing Systems
El-Hadedy, M., Guo, X., Margala, M., Stan, M., Skadron, K.
J. Signal Proc. Sys.
Vol. 88 · Journal
[42]
Accelerating Weeder: A DNA Motif Search Tool Using the Micron Automata Processor and FPGA
Wang, Q., El-Hadedy, M., Skadron, K., Wang, K.
IEICE Trans.
Vol. E100-D · Journal
[43]
A Compliant Mechanism for Inspecting Extremely Confined Spaces
Mascareñas, D., Moreu, F., Cantu, P., Shields, D., Wadden, J., El-Hadedy, M., Farrar, C.
Smart Materials & Structures
Vol. 26 · Journal
[44]
RE-HASE: Regular-Expressions Hardware Synthesis Engine
El-Hadedy, M., Guo, X., Huang, X., Margala, M.
H2RC / SC17
Workshop
[45]
PPE-ARX: Area- and Power-Efficient VLIW Processing Element for IoT Crypto-Systems
El-Hadedy, M., Guo, X., Stan, M., Skadron, K.
NASA / ESA AHS
California
[46]
On Accelerating Pair-HMM Computations in Programmable Hardware
Banerjee, S. S., El-Hadedy, M., et al.
FPL
Ghent
[47]
Reco-CPIOT: Reconfigurable Crypto-Processor for Secure IoT
El-Hadedy, M., Formicola, V., Kourfali, A., Stroobandt, D., Skadron, K.
RFPL / FPL
Workshop
2016 · 3 entries
[48]
A 16-bit Reconfigurable Encryption Processor for Pi-Cipher
El-Hadedy, M., Mihajloska, H., Gligoroski, D., Kulkarni, A., Stroobandt, D., Skadron, K.
RAW / IPDPS
Best Paper
[49]
Generating Efficient Pseudo-Random Behavior on Micron's Automata Processor
Wadden, J., Brunelle, N., Wang, K., El-Hadedy, M., et al.
IEEE ICCD
Conference
[50]
RAPID: Accelerating Pattern Search with Reconfigurable Hardware
Angstadt, K., Wadden, J., Huang, X., El-Hadedy, M., et al.
SRC TECHCON
Best Paper · Session
2015 · 3 entries
[51]
Programmable Processing Element for Crypto-Systems on FPGAs
El-Hadedy, M., Skadron, K., Mihajloska, H., Gligoroski, D.
HEART
Boston
[52]
Hardware Overhead Analysis of Programmability in ARX Crypto Processing
El-Hadedy, M., Skadron, K.
HASP
Portland
[53]
Area Efficient Reconfigurable Processing Element for Crypto-Systems
El-Hadedy, M., Skadron, K.
DAC
San Francisco
2014 · 1 entry
[54]
Π-Cipher: Authenticated Encryption for Big Data
Gligoroski, D., et al., El-Hadedy, M.
NordSec
Conference
2011 · 1 entry
[55]
An Efficient Authorship Protection Scheme for Shared Multimedia Content
El-Hadedy, M., Pitsilis, G., Knapskog, S. J.
ICIG
Conference
2010 · 4 entries
[56]
Compact Implementation of Blue Midnight Wish-256 Hash Function on Xilinx FPGA
El-Hadedy, M., Gligoroski, D., Knapskog, S. J., Margala, M.
J. Information Assurance
Vol. 5 · Journal
[57]
Resource-Efficient Implementation of Blue Midnight Wish-256
El-Hadedy, M., Margala, M., Gligoroski, D., Knapskog, S. J.
IAS
Atlanta
[58]
Performance and Area Efficient Transpose Memory Architecture
El-Hadedy, M., Purohit, S., Margala, M., Knapskog, S. J.
NASA / ESA AHS
Anaheim
[59]
Low Latency Transpose Memory for High Throughput Signal Processing
El-Hadedy, M., Purohit, S., Margala, M., Knapskog, S. J.
NEWCAS
Montreal
2009 · 2 entries
[60]
Low Area FPGA and ASIC Implementations of Blue Midnight Wish-256
El-Hadedy, M., Gligoroski, D., Knapskog, S. J.
ICCES
Conference
[61]
Low Area Implementation of Blue Midnight Wish-256 for FPGA
El-Hadedy, M., Gligoroski, D., Knapskog, S. J.
INCoS
Barcelona
2006 · 1 entry
[62]
Comparisons of DCT-Based and DWT-Based Watermarking Techniques
Saleh, H. I., El-Hadedy, M., Ashour, M. A., Aboelsaud, M. A.
Int J Sci Research
Vol. 16 · Journal
Patent (also issued 2021) · 1 entry
[63]
Reconfigurable Crypto-Processor for Secure IoT Applications
El-Hadedy, M., Hwu, W.-M., Skadron, K. — U.S. Patent 11,157,275 — 2021
Patent
UVA · UIUC
— Invited Talks & Keynotes

Where the work is being heard.

Secure Edge Intelligence for Autonomous Systems: Real-Time NLP Teleoperations & Post-Quantum Telemetry on K3s
Mohamed El-Hadedy — Invited Talk, ARCHIDE: 2nd Workshop on Architecture Design Methodologies and Ecosystems for HPC and Scientific Edge Computing
Lawrence Berkeley
National Lab · 2025
Resource-Efficient Cryptography and Secure IoMT: Enhancing Embedded Systems with Post-Quantum and Multi-Clock Domain Optimizations
Mohamed El-Hadedy — Invited Talk, ARCHIDE: 1st Workshop on Architecture Design Methodologies and Ecosystems for HPC and Scientific Edge Computing
Lawrence Berkeley
National Lab · 2024
— Full bibliography
View on Google Scholar →
Dr. Mohamed El-Hadedy, Founder and CEO of RecoIoT LLC, tenured Associate Professor at Cal Poly Pomona, director of the Reconfigurable Space Computing Lab
— Founder & CEO
Dr. Mohamed El-Hadedy
RecoIoT LLC · Cal Poly Pomona
— Leadership

Building real systems for places software alone won't reach.

"I want my hardware to deserve its name. If a system is called HORUS, then it had better watch. If it is called MA'AT, it had better keep order. The naming is a promise to the people who depend on it."

Dr. Mohamed El-Hadedy is the founder and CEO of RecoIoT LLC and a tenured Associate Professor in the Department of Electrical & Computer Engineering at California State Polytechnic University, Pomona, where he directs the Reconfigurable Space Computing Lab (RSCL@CPP).

His research sits at the intersection of reconfigurable computing, embedded security, flight software, and mission-driven autonomy. What makes the work distinctive is that it does not stop at algorithms or simulations — it produces complete systems: FPGA and MPSoC prototypes, Kubernetes/edge testbeds, flight-software integrations, drone platforms, cryptographic services, sensor pipelines, and defense-relevant autonomy experiments. SEKHMET won Best Paper at NG-RES 2026/HiPEAC. HORUS turns unavoidable multirotor blade-pass noise into an acoustic side-channel for GPS- and RF-denied swarm awareness. MEHEN (under review at IEEE Space Computing) makes programmable fabric the backend of an F′ flight-software security component — not just hardware acceleration, but operationally visible security services integrated into real flight workflows. The core pattern across the work is capability creation, not incremental exercises.

Mohamed earned his Ph.D. from the Norwegian University of Science and Technology (NTNU), with a dissertation in cryptographic hardware co-design. He holds a Master's and Bachelor's in Electronics Engineering from Mansoura University, Egypt. Before academic research, from 2004 to 2008, he served as a Research Scientist at the Egyptian Nuclear Research Reactor — a foundation that informs his ongoing work on radiation-tolerant computing, single-event-effects (SEE), and trustworthy electronics for space.

After NTNU he joined Atmel Norway AS as a Senior Design Engineer, working on production microcontroller and FPGA silicon — the industry foundation that grounds every prototype RecoIoT builds today in real chip-design discipline. He then returned to academia as Postdoctoral Fellow at the University of Virginia and Senior Research Scientist at the University of Illinois Urbana-Champaign (UIUC) in collaboration with Wen-Mei Hwu. RecoIoT LLC was founded in 2017 to translate that research-and-industry lineage into deliverable hardware for U.S. defense and space programs.

His record shows sustained, mission-aligned achievement: continuous federal support since 2017 from the Air Force Research Laboratory, U.S. Army Research Office, U.S. Navy NEEC and ONR, NSWC Corona, NASA, and Lawrence Berkeley National Lab — cumulative awards exceeding $5 million. Three issued U.S. patents in reconfigurable cryptographic processing and transposition-memory architecture, plus a fourth filed for a compliant inspection mechanism developed at Los Alamos National Laboratory. Three Best Paper Awards across NG-RES/HiPEAC 2026, RAW/IPDPS 2016, and SRC TECHCON 2016. Third Place at the 2025 IEEE Telepresence Competition in Perth, Australia. Invited talks at LBNL in 2024 and 2025. More than seventy peer-reviewed papers. Mentor of multiple NASA MINDS finalist and award-winning teams. Senior Member of both IEEE and ACM.

His operating thesis is straightforward: the strongest defense systems are not the ones with the most software, but the ones with the most verifiable silicon — hardware that can be reasoned about, audited, and trusted at the component level. RecoIoT is built around that belief.

Doctorate
Ph.D., NTNUNorwegian Univ. of Science & Technology
Foundation
M.Sc. & B.Sc.Mansoura University, Egypt
Early Career
Research ScientistEgyptian Nuclear Research Reactor · 2004–2008
Academic Home
Cal Poly PomonaTenured Associate Professor, ECE
Memberships
IEEE Senior MemberACM Senior Member
Patents Issued
3 U.S. Patents+1 filed (LANL)
Industry
Atmel Norway ASSenior Design Engineer
Mentorship
NASA MINDSMultiple finalist & award-winning teams
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Talk to us about real systems.

We're always open to honest conversations — about SBIR/STTR collaborations, federal research partnerships, edge deployments, or just hard problems in reconfigurable computing, post-quantum cryptography, or trustworthy autonomy. If something here resonates with what you're building, write to us.

Principal
Dr. Mohamed El-Hadedy
CEO & Founder, RecoIoT LLC
Location
Pomona, California
Founded 2017
SBC Identifier
SBC_002671100